1. Technical Field
The present disclosure relates to a layout of a semiconductor integrated circuit device. More particularly, the present disclosure relates to a technique effective for suppressing latch-up with an area of a semiconductor integrated circuit being reduced.
2. Description of the Related Art
Latch-up recently becomes a significant problem with an advance of microfabrication of a pattern in a manufacturing process of a semiconductor integrated circuit device. The latch-up means a phenomenon in which, since a bipolar parasitic transistor formed in a semiconductor integrated circuit device becomes a thyristor structure, this thyristor is turned on by a trigger such as serge, and excess current keeps on flowing. This phenomenon will be described with reference to FIG. 12.
FIG. 12 is a diagram illustrating a sectional structure of a conventional semiconductor integrated circuit device. N-type well Wn1 and P-type well Wp1 are formed on P-type substrate Sp. P-type diffusion regions Dpd1 and Dps1 and polysilicon PO1 on N-type well Wn1 respectively form a drain, a source, and a gate of P-type MOS transistor Tp1.
Substrate contact Dnn1 supplies a substrate potential of P-type MOS transistor Tp1. Substrate contact Dnn1 and P-type diffusion region Dps1 that is the source of P-type MOS transistor Tp1 are connected to power-supply potential VDD. N-type diffusion regions Dnd1 and Dns1 and polysilicon PO2 on P-type well Wp1 respectively form a drain, a source, and a gate of N-type MOS transistor Tn1. Substrate contact Dpp1 supplies a substrate potential of N-type MOS transistor Tn1. Substrate contact Dpp1 and N-type diffusion region Dns1 that is the source of N-type MOS transistor Tn1 are connected to ground potential VSS.
P-type parasitic bipolar transistor Bp1 and N-type parasitic bipolar transistor Bn1 are generated in the conventional semiconductor integrated circuit. However, node N2 is kept to be power-supply potential VDD by substrate contact Dnn1. Node N1 is kept to be ground potential VSS by substrate contact Dpp1. Each of P-type parasitic bipolar transistor Bp1 and N-type parasitic bipolar transistor Bn1 is connected to a base of the corresponding bipolar transistor. Accordingly, the bipolar transistor is not turned on, so that current does not generally flow through N-type well Wn1, P-type well Wp1, and P-type substrate Sp.
On the other hand, when current I forcibly flows in P-type substrate Sp due to external force such as serge or substrate noise, current flows through node N1. The potential of node N1 increases, whereby N-type parasitic bipolar transistor Bn1 is turned on. Then, current flows through node N2, so that the potential of node N2 decreases. Therefore, P-type parasitic bipolar transistor Bp1 is also turned on, whereby current keeps on flowing through node N1. The phenomenon in which high current keeps on flowing in the semiconductor integrated circuit as described above is called latch-up. The latch-up may entail breakdown of an element required for a CMOS operation.
There is a method for suppressing the latch-up in which as many substrate contacts as possible are assured to prevent an increase in the potential of node N1 and a decrease in the potential of node N2. There is another method in which a space d between the substrate contact region and the diffusion region of the CMOS transistor is reduced to decrease resistance in order that, even if current flows, the increase in the potential of node N1 and the decrease in the potential of node N2 are suppressed.
In a conventional semiconductor integrated circuit, a substrate contact region is regularly disposed beforehand on a transistor array. Then, a circuit element required for the operation of the semiconductor integrated circuit is disposed on a remaining region on the transistor array other than the region where the substrate contact region is disposed. Elements, such as a decoupling capacitance element suppressing power supply noise of the semiconductor integrated circuit, which do not contribute to a logical operation of the semiconductor integrated circuit are disposed on a region (hereinafter referred to as a margin region) other than the substrate contact region and the region where the circuit element required for the operation is disposed. There is another method in which nothing is disposed on the margin region. Such semiconductor integrated circuit devices have been generally known (U.S. Pat. No. 6,560,753).
There has also been known a semiconductor integrated circuit device including a substrate contact region for preventing latch-up formed on a margin region (Unexamined Japanese Patent Publication No. H11-026590).